1. Field of the Invention
The invention relates to a piece of electronic equipment having a display device, and particularly to a piece of electronic equipment having a display device in which display data and operation data are stored in a one-chip RAM and a soft timer program is usable.
2. Description of Related Art
A piece of electronic equipment having a display device, for example, a word processor having a CRT, a liquid crystal device (LCD) display or other type of display device has been conventionally equipped with a RAM having a text area for storing a work area which is used for data operation by a microprocessor unit (MPU) and document data, and a video RAM (V-RAM) provided as another separate chip which is designed independently of the RAM and serves to store only display data.
FIG. 4 is a block diagram showing a conventional word processor as described above. The conventional word processor 80 shown in FIG. 4 includes a display device 81, a keyboard 82, an external storage device 83, a print device 84 and a control device C8. The display device 81 comprises a liquid crystal device (LCD) display 85 and an LCD controller 86 for controlling the display operation of the LCD display 85. The control device C8 comprises an MPU 96, a ROM 97, a RAM 98, a V-RAM 92, a timing control circuit 95, an input/output interface 93 and a bus line 94.
In the conventional word processor 80 thus structured, the access operation of the V-RAM 92 is carried out as follows.
First, the MPU 96 writes display data into the V-RAM 92 through the bus line 94 and the input/output interface 93. Further, the LCD controller 86 periodically reads out from the V-RAM 92 the display data which have been written by the MPU 96, and outputs the data to the LCD display 85 for display.
Since the MPU 96 and the LCD controller 86 are operated in asynchronism with each other, the MPU 96 and the LCD controller 86 may accidentally access the V-RAM 92 at the same time unless an access timing to the V-RAM 92 is controlled between the MPU 96 and the LCD controller 86 using a suitable means. Once such a case occurs, the MPU 96 may write or read erroneous data into or from the V-RAM 92, resulting in disturbance of the display operation of the LCD display 85. This is because when the V-RAM 92 is supplied with different addresses from the MPU 96 and the LCD controller 86, an erroneous address of the V-RAM 92 is accessed, or the write-in or read-out data of the MPU 96 for the V-RAM 92 are overlapped with read-out data which are read out from the V-RAM 92 by the LCD controller 86.
Therefore, a timing control circuit 95 is provided so that the access of the LCD controller 86 has priority over the access of the MPU 96 because the LCD controller 86 periodically accesses the V-RAM 92, whereby the MPU 96 and the LCD controller 86 are prevented from accessing the V-RAM 92 at the same time.
That is, when the MPU 96 needs access to the V-RAM 92, the MPU 96 first outputs to the timing control circuit 95 a signal indicating an access requirement thereof to the V-RAM 92. Upon input of the signal, the timing control circuit 95 checks the current status of the LCD controller 86. If the LCD controller 86 is reading out data from the V-RAM 92 at that time, the timing control circuit 95 outputs to the MPU 96 an access waiting signal which instructs the MPU 96 to wait for access to the V-RAM 96 until the read-out operation of the LCD controller 86 for the V-RAM 92 is completed. Upon receipt of the waiting signal, the MPU 96 waits for access to the V-RAM 92. When the read-out operation of the LCD controller 86 for the V-RAM 92 is completed, the timing control circuit 95 ceases the output of the waiting signal to the MPU 96. In response to the stopping of the waiting signal, the MPU 96 releases its waiting or standby state to carry out the read-out or write-in operation of new data for the V-RAM 92.
However, the conventional word processor 80, as described above, must be equipped with not only the RAM 98 for storing both the operation data and the document data, but also the V-RAM 92 for storing display data as a chip memory which is provided separately from the RAM 98. That is, two RAM chips must be provided, resulting in an increased cost of the device.